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Xilinx VHDL UART Example

Overview

The Xilinx VHDL UART project is an example project for the Papilio One FPGA development board. The project is a Xilinx reference design that has been conveniently packaged up for the Papilio One. There is also a set of tutorial screencasts that have been recorded to for this design.

The Xilinx VHDL UART example provides a VHDL example of how to implement a 3Mb/s UART core on the Papilio One. This example is extremely compact and fast.

This is a community example project, so please feel free to extend the code, make it your own, and share back with the community. Please feel free to share any information you discover about this code in the Wiki so others can benefit from your explorations.

Quick Start

Requirements

Papilio One FPGA development board
- Papilio One 250K or
- Papilio One 500K

Downloads

Xilinx VHDL UART bitstreams - Download these directly to your board using the Papilio Loader to instantly see the project run.
- Papilio One 250K bitstream
- Papilio One 500K bitstream
Source code - The source code for the Xilinx VHDL UART project is ready to synthesize for the Papilio One 250K and 500K boards. Open the project with the free Xilinx ISE Webpack software.
- Xilinx VHDL UART 1.0 Source Code
- Picoblaze source code from Xilinx

Documentation

When you download the Picoblaze processor from Xilinx you will find a "Uart_Manual.pdf" file with more information.
There is a publically accessible app note (XAPP223) that provides much of the same information as the pdf above.

Tutorial Videos

View all of the Tutorial Video series here.

Attribution

The Xilinx VHDL UART example project was downloaded from Xilinx.com and is a part of the Picoblaze processor. The project has a proprietory license and requires an individual agreement with Xilinx. The source code for the Picoblaze project must be downloaded directly from Xilinx.

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Description
Example code for using the Xilinx VHDL UART.
Developer Info
Jack Gassett
Trove Categorization
Development Status: 5 - Production/Stable Intended Audience: FPGA Developer, HDL License: Creative Commons Attribution Spoken Language: English Topic: FPGA Projects, Papilio One
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FPGA - Xilinx VHDL UART Example