Hello Ronald,

It wasn't by chance this (http://flash-plaice.wikispaces.com/) project was it? When I tried to submit a story on Slashdot I noticed that project had already been submitted.

Yes the 4k is a result of using internal BRAM, the 250E chip has 6K of BRAM available. So I have several options to add more memory to the design. With the 250E chip I can use the Xilinx MIG tool to give access to all 6K of BRAM. I didn't do that initially because I wanted the source code to be clear to people who wanted to look at the design. The MIG creates a Macro which hides the details of the VHDL. I also intend to offer a Butterfly Heavy board which will have the 500E chip which has something like 16K of BRAM. Finally I have a design with SDRAM pretty much finished and ready to go, I'm just waiting to finish the Butterfly Specification which will implement the concept of "Wings" for peripherals. Once I am done with that and the first couple of Wings to provide an example I will probably finish up the SDRAM design which will make several MB of RAM available. Assuming I'm succesful in making it work. I think I should be able to, I've been able to make a SDRAM design work 98% in the past. I had an issue with one address line that was to close to a clock line.

Clocking comes from the external 8MHz clock that is passed through a DCM which turns it into a 100MHz clock. I choose a low 8MHz clock for the Butterfly Platform in order to keep signals on the board low frequency. High frequency clocks can be generated with DCM's inside the chip without hitting the board.

Jack.