Jack, I'm sorry to dissapoint you, but that is not my project, actually I never had the chance to publish it.
Well, I will be working on it again in the days to come so may be we can discuss  things that would came up, I also would need to change my target platform because starter board are not that cheap, yours look like a very good aproach, also the ones on sparkfun.

I just remember that I was limited on RAM resources because I had the patern generattor in the same FPGA, so I dont really understand your 4K boundary, also I dont know about MIG, I actually use Verilog code (a synchronous access set of registers) that is inferred as a block ram, and size only depends on the length of the memory index, that is of course a parameter. The platform I was using had an external sdram I cannot remember if we make it work, but I do remember that the chip had timing limitations itself.

What about your critical path?...why is that you only reach the 100Mhz....It would be nice to reach faster timing, of course only if it doesnt goes against storage. Mine was tested only at 50 Mhz, and I think it would make 75 but the critical path was on the pattern generator that had a function that included some aritmethics and I know even that could be improved, well I guess that external lines should have an impact on timing too...¿?

About DCM, can you take multiple clocks from one?...can you dinamically change the speed? I dont think that is possible...I was thinking on using 2 clocks, a fixed one for control and a external voltage controlled oscillator for capturing data.

My interface was more rudimentary,  we coded a C program control the machine and  among other stuff to retrieve the stored data via RS232 and then output to text, then another program converted it to VCD wich I could draw on GTKWave or alike. That way the code was easily portable and I tested on linux and windows.

Cheers,
Ronald